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    Author information
    First name: Donghyuk
    Last name: Lee
    DBLP: 00/10253
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    Conference paper
    Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu.
    Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization.
    Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, Antibes Juan-Les-Pins, France, June 14-18, 2016 2016 (0) 2016
    Conference paper
    Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, Onur Mutlu.
    Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.
    2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016 2016 (0) 2016
    Conference paper
    Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu.
    ChargeCache: Reducing DRAM latency by exploiting row access locality.
    2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016 2016 (0) 2016
    Journal article
    Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu.
    RowHammer: Reliability Analysis and Security Implications.
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu.
    Adaptive-Latency DRAM (AL-DRAM).
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu.
    Tiered-Latency DRAM (TL-DRAM).
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu.
    Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses.
    CoRR 2016, Volume 0 (0) 2016
    Conference paper
    Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu.
    Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost.
    TACO 2015, Volume 12 (0) 2016
    Conference paper
    Donghyuk Lee, Lavanya Subramanian, Rachata Ausavarungnirun, Jongmoo Choi, Onur Mutlu.
    Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM.
    2015 International Conference on Parallel Architecture and Compilation, PACT 2015, San Francisco, CA, USA, October 18-21, 2015 2015 (0) 2015
    Conference paper
    Vivek Seshadri, Kevin Hsieh, Amirali Boroumand, Donghyuk Lee, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry.
    Fast Bulk Bitwise AND and OR in DRAM.
    Computer Architecture Letters 2015, Volume 14 (0) 2015
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