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    First name: Donghyuk
    Last name: Lee
    DBLP: 00/10253
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    Journal article
    Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry.
    Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM.
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Saugata Ghose, Onur Mutlu.
    Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.
    CoRR 2016, Volume 0 (0) 2016
    Conference paper
    Samira Manabi Khan, Donghyuk Lee, Onur Mutlu.
    PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM.
    46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2016, Toulouse, France, June 28 - July 1, 2016 2016 (0) 2016
    Conference paper
    Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu.
    BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling.
    IEEE Trans. Parallel Distrib. Syst. 2016, Volume 27 (0) 2016
    Conference paper
    Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu.
    Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization.
    Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, Antibes Juan-Les-Pins, France, June 14-18, 2016 2016 (0) 2016
    Conference paper
    Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, Onur Mutlu.
    Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.
    2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016 2016 (0) 2016
    Conference paper
    Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu.
    ChargeCache: Reducing DRAM latency by exploiting row access locality.
    2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016 2016 (0) 2016
    Journal article
    Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu.
    RowHammer: Reliability Analysis and Security Implications.
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu.
    Adaptive-Latency DRAM (AL-DRAM).
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu.
    Tiered-Latency DRAM (TL-DRAM).
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu.
    Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses.
    CoRR 2016, Volume 0 (0) 2016
    Conference paper
    Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu.
    Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost.
    TACO 2015, Volume 12 (0) 2016
    Conference paper
    Donghyuk Lee, Lavanya Subramanian, Rachata Ausavarungnirun, Jongmoo Choi, Onur Mutlu.
    Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM.
    2015 International Conference on Parallel Architecture and Compilation, PACT 2015, San Francisco, CA, USA, October 18-21, 2015 2015 (0) 2015
    Conference paper
    Vivek Seshadri, Kevin Hsieh, Amirali Boroumand, Donghyuk Lee, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry.
    Fast Bulk Bitwise AND and OR in DRAM.
    Computer Architecture Letters 2015, Volume 14 (0) 2015
    Journal article
    Donghyuk Lee, Gennady Pekhimenko, Samira Manabi Khan, Saugata Ghose, Onur Mutlu.
    Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface.
    CoRR 2015, Volume 0 (0) 2015
    Journal article
    Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu.
    The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity.
    CoRR 2015, Volume 0 (0) 2015
    Conference paper
    Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu.
    Adaptive-latency DRAM: Optimizing DRAM timing for the common-case.
    21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA, February 7-11, 2015 2015 (0) 2015
    Conference paper
    Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu.
    The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost.
    32nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea, October 19-22, 2014 2014 (0) 2014
    Conference paper
    Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu.
    Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.
    ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, June 14-18, 2014 2014 (0) 2014
    Conference paper
    Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu.
    Improving DRAM performance by parallelizing refreshes with accesses.
    20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014 2014 (0) 2014
    Conference paper
    Samira Manabi Khan, Donghyuk Lee, Yoongu Kim, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu.
    The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study.
    ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS '14, Austin, TX, USA - June 16 - 20, 2014 2014 (0) 2014
    Conference paper
    Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry.
    RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization.
    The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013 2013 (0) 2013
    Journal article
    Hongyi Xin, Donghyuk Lee, Farhad Hormozdiari, Samihan Yedkar, Onur Mutlu, Can Alkan.
    Accelerating read mapping with FastHASH.
    BMC Genomics 2013, Volume 14 (0) 2013
    Conference paper
    Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu.
    Tiered-latency DRAM: A low latency and low cost DRAM architecture.
    19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013 2013 (0) 2013
    Conference paper
    Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu.
    A case for exploiting subarray-level parallelism (SALP) in DRAM.
    39th International Symposium on Computer Architecture (ISCA 2012), June 9-13, 2012, Portland, OR, USA 2012 (0) 2012
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