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    Author information
    First name: Vivek
    Last name: Seshadri
    DBLP: 117/0561
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    Journal article
    Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu.
    Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.
    POMACS 2017, Volume 1 (0) 2017
    Conference paper
    Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu.
    Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.
    Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Urbana-Champaign, IL, USA, June 05 - 09, 2017 2017 (0) 2017
    Journal article
    Vivek Seshadri, Onur Mutlu.
    Chapter Four - Simple Operations in Memory to Reduce Data Movement.
    Advances in Computers 2017, Volume 105 (0) 2017
    Journal article
    Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu.
    Tiered-Latency DRAM (TL-DRAM).
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu.
    Adaptive-Latency DRAM (AL-DRAM).
    CoRR 2016, Volume 0 (0) 2016
    Conference paper
    Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu.
    ChargeCache: Reducing DRAM latency by exploiting row access locality.
    2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016 2016 (0) 2016
    Conference paper
    Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu.
    BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling.
    IEEE Trans. Parallel Distrib. Syst. 2016, Volume 27 (0) 2016
    Journal article
    Vivek Seshadri, Onur Mutlu.
    The Processing Using Memory Paradigm: In-DRAM Bulk Copy, Initialization, Bitwise AND and OR.
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Saugata Ghose, Onur Mutlu.
    Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.
    CoRR 2016, Volume 0 (0) 2016
    Journal article
    Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry.
    Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM.
    CoRR 2016, Volume 0 (0) 2016
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