Publications :: Search

Show author

On this page you see the details of the selected author.

    Author information
    First name: Yale N.
    Last name: Patt
    DBLP: p/YaleNPatt
    Rating: (not rated yet)
    Bookmark:

    Below you find the publications which have been written by this author.

    Show item 1 to 48 of 48  
    Select a publication
    Show Title Venue Rating Date PDF
    Conference paper
    Milad Hashemi, Onur Mutlu, Yale N. Patt.
    Continuous runahead: Transparent hardware acceleration for memory intensive workloads.
    49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016 2016 (0) 2016
    Conference paper
    Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt.
    Accelerating Dependent Cache Misses with an Enhanced Memory Controller.
    43rd ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2016, Seoul, South Korea, June 18-22, 2016 2016 (0) 2016
    Conference paper
    Onur Mutlu, Richard A. Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe.
    Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.
    IEEE Micro 2016, Volume 36 (0) 2016
    Conference paper
    José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt.
    Utility-based acceleration of multithreaded applications on asymmetric CMPs.
    The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013 2013 (0) 2013
    Conference paper
    Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt.
    Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems.
    ACM Trans. Comput. Syst. 2012, Volume 30 (0) 2012
    Conference paper
    José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt.
    Bottleneck identification and scheduling in multithreaded applications.
    Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2012, London, UK, March 3-7, 2012 2012 (0) 2012
    Conference paper
    Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt.
    Parallel application memory scheduling.
    44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011 2011 (0) 2011
    Conference paper
    Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt.
    Improving GPU performance via large warps and two-level warp scheduling.
    44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011 2011 (0) 2011
    Conference paper
    Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt.
    Prefetch-Aware Memory Controllers.
    IEEE Trans. Computers 2011, Volume 60 (0) 2011
    Conference paper
    Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt.
    Prefetch-aware shared resource management for multi-core systems.
    38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA 2011 (0) 2011
    Journal article
    Yale N. Patt, Onur Mutlu.
    Top Picks [Guest editors' introduction].
    IEEE Micro 2011, Volume 31 (0) 2011
    Journal article
    M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt.
    Data Marshaling for Multicore Systems.
    IEEE Micro 2011, Volume 31 (0) 2011
    Conference paper
    M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt.
    Data marshaling for multi-core architectures.
    37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France 2010 (0) 2010
    Journal article
    M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt.
    Accelerating Critical Section Execution with Asymmetric Multicore Architectures.
    IEEE Micro 2010, Volume 30 (0) 2010
    Conference paper
    Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt.
    Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems.
    Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010 2010 (0) 2010
    Conference paper
    Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt.
    Improving memory bank-level parallelism in the presence of prefetching.
    42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA 2009 (0) 2009
    Conference paper
    Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt.
    Coordinated control of multiple prefetchers in multi-core systems.
    42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA 2009 (0) 2009
    Conference paper
    Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert S. Cohn.
    Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware.
    IEEE Trans. Computers 2009, Volume 58 (0) 2009
    Conference paper
    José A. Joao, Onur Mutlu, Yale N. Patt.
    Flexible reference-counting-based hardware acceleration for garbage collection.
    36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA 2009 (0) 2009
    Conference paper
    Eiman Ebrahimi, Onur Mutlu, Yale N. Patt.
    Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems.
    15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA 2009 (0) 2009
    Conference paper
    M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt.
    Accelerating critical section execution with asymmetric multi-core architectures.
    Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2009, Washington, DC, USA, March 7-11, 2009 2009 (0) 2009
    Conference paper
    Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt.
    Prefetch-Aware DRAM Controllers.
    41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy 2008 (0) 2008
    Conference paper
    Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt.
    Performance-aware speculation control using wrong path usefulness prediction.
    14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA 2008 (0) 2008
    Conference paper
    José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt.
    Improving the performance of object-oriented languages with dynamic predication of indirect jumps.
    Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008 2008 (0) 2008
    Journal article
    José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt.
    Dynamic Predication of Indirect Jumps.
    Computer Architecture Letters 2008, Volume 7 (0) 2007
    Conference paper
    Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt.
    Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication.
    IEEE Micro 2007, Volume 27 (0) 2007
    Conference paper
    José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt.
    Dynamic Predication of Indirect Jumps.
    Computer Architecture Letters 2007, Volume 6 (0) 2007
    Conference paper
    Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert S. Cohn.
    VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization.
    34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA 2007 (0) 2007
    Conference paper
    Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt.
    Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers.
    13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA 2007 (0) 2007
    Conference paper
    Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt.
    Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors.
    Fifth International Symposium on Code Generation and Optimization (CGO 2007), 11-14 March 2007, San Jose, California, USA 2007 (0) 2007
    Conference paper
    Onur Mutlu, Hyesoon Kim, Yale N. Patt.
    Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses.
    IEEE Trans. Computers 2006, Volume 55 (0) 2006
    Conference paper
    Onur Mutlu, Hyesoon Kim, Yale N. Patt.
    Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance.
    IEEE Micro 2006, Volume 26 (0) 2006
    Conference paper
    Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark.
    Wish Branches: Enabling Adaptive and Aggressive Predicated Execution.
    IEEE Micro 2006, Volume 26 (0) 2006
    Conference paper
    Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt.
    Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths.
    39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA 2006 (0) 2006
    Conference paper
    Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt.
    A Case for MLP-Aware Cache Replacement.
    33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA 2006 (0) 2006
    Conference paper
    Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt.
    2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set.
    Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 26-29 March 2006, New York, New York, USA 2006 (0) 2006
    Conference paper
    Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt.
    An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.
    IEEE Trans. Computers 2005, Volume 54 (0) 2005
    Conference paper
    Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt.
    Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References.
    International Journal of Parallel Programming 2005, Volume 33 (0) 2005
    Conference paper
    Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt.
    On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor.
    Computer Architecture Letters 2005, Volume 4 (0) 2005
    Conference paper
    Onur Mutlu, Hyesoon Kim, Yale N. Patt.
    Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns.
    38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain 2005 (0) 2005
    Conference paper
    Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt.
    Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution.
    38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain 2005 (0) 2005
    Conference paper
    Onur Mutlu, Hyesoon Kim, Yale N. Patt.
    Techniques for Efficient Processing in Runahead Execution Engines.
    32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA 2005 (0) 2005
    Conference paper
    Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt.
    Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors.
    2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings 2005 (0) 2005
    Conference paper
    Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt.
    Understanding the effects of wrong-path memory references on processor performance.
    Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction with the 31st International Symposium on Computer Architecture 2004, Munich, Germany, June 20, 2004 2004 (0) 2004
    Conference paper
    Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt.
    Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance.
    16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 27-29 October 2004, Foz do Iguacu, Brazil 2004 (0) 2004
    Conference paper
    David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt.
    Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery.
    37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA 2004 (0) 2004
    Conference paper
    Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt.
    Runahead Execution: An Effective Alternative to Large Instruction Windows.
    IEEE Micro 2003, Volume 23 (0) 2003
    Conference paper
    Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt.
    Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors.
    HPCA 2003 (0) 2003
    Show item 1 to 48 of 48  

    Your query returned 48 matches in the database.