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Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.

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    Publication properties
    Title: Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.
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    Date: 2017
    Publication type: Journal article
    Authors:
    No. First name Last name Show
    1. Donghyuk Lee
    2. Samira Manabi Khan
    3. Lavanya Subramanian
    4. Saugata Ghose
    5. Rachata Ausavarungnirun
    6. Gennady Pekhimenko
    7. Vivek Seshadri
    8. Onur Mutlu
    Download (by DOI): 10.1145/3084464
    BibTeX: journals/pomacs/LeeKSGAPSM17
    DBLP: db/journals/pomacs/pomacs1.html#LeeKSGAPSM17
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    Journal
    Name: POMACS
    Year: 2017
    Volume: 1
    Number: 1
    DBLP: db/journals/pomacs/pomacs1.html